Description of the length of the starting pulse width of the control timing of the first-line serial port of the GY148A voice chip

GY148A first-line serial port details

The GY148A voice chip supports one-line serial port control and single-line timing logic, so there are two details to pay attention to.

Requirements for the length of the initial pulse width.
Pulse width distribution of data 0 and data 1.

Timing requirements for front-line communications

The operation is very simple. First, pull the data line DATA, that is, ONELINE, low for 6ms, and then send 8-bit data. The low bit is sent first, and then the high bit is sent. Use the ratio of high and low levels to represent the value of each data bit.

Note: The high level must be in the front and the low level in the back.

It is recommended to use 200us: 600us. Value range: narrow pulse = [150us–400us] wide pulse [500us–1000us].

Pay attention to using 3:1 and 1:3 level ratio to ensure stable communication.

Things to note about start signals

Customers still have some doubts about the start signal during use. Here we will give a detailed explanation. The start signal is divided into two uses:

The first use: command start data recognition, the ONELINE IO port set inside the GY148A chip is weakly pulled up, and has the function of capturing

After capturing the falling edge, it is considered that data is coming. At this time, it waits for the rising edge until the length of 6ms is met before the subsequent data is considered to be real data. This is the principle.

The second use: used to wake up the GY148A chip. Because the chip has a mechanism to enter standby after being idle for 5 seconds, so when data comes from the external serial port, it wakes up first and then receives the data.

The test details are as follows:

Start signal length: 6.55ms = can trigger playback

Start signal length: 6.85ms = The start signal is too long and cannot be played in standby mode

Start signal length: 5.66ms = can trigger playback

In short: the low-level length of the start signal, uniformly stipulated here, must be between 5.5ms—–6.5ms. 6ms is recommended, and the error can be controlled at 10%.

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